1. Technical Field
This invention generally relates to methods and apparatus for a microprocessor to perform non-cacheable accesses in a computer system, and more specifically relates to a method and apparatus for decreasing the access time to non-cacheable address space by detecting an access to non-cacheable address space and commencing a bus cycle to access the data before the cache indicates a cache miss.
2. Background Art
The use of cache memory in computer systems offers numerous advantages that increase system performance. System memory in a computer is typically slower than the time in which the processor can access the data, requiring the Insertion of one or more wait states. Cache memory is typically small and very fast (no wait states), and may be interposed between a local processor bus and a system bus. The cache typically contains a copy of instructions and/or data from system memory that the processor accesses most frequently. If the instruction or data the processor needs is located in cache memory, the cache signals a "hit," and the instruction or data is accessed at the cache. If the cache does not contain the needed instruction or data, the cache signals a "miss," and the instruction or data is accessed at the system memory. The isolation provided by the cache memory system allows the processor to continue processing from its cache memory on its local bus so long as it receives "hits" while other devices have control of the system bus.
Not all transfers within a computer system are "cacheable," i.e., should be stored in the cache. Specifically, transfers between the processor and devices on an expansion bus in a typical microcomputer system are generally non-cacheable. In addition, certain portions of system memory may be mapped as non-cacheable. Cacheable and non-cacheable accesses are typically defined by the system memory map, with certain addresses defined as cacheable and other addresses defined as non-cacheable. Thus, the cache stores and retrieves data in its memory for cacheable addresses while not storing or retrieving data for non-cacheable addresses.
Various methods of distinguishing cacheable address space from non-cacheable address space are known. One such method is disclosed in U.S. Pat. No. 5,247,642, "Apparatus for Determining Cacheability of a Memory Address to Provide Zero Wait State Operation in a Computer System" (issued Sep. 1993 to Kadlec et al. and assigned to AST Research, Inc.), which is incorporated herein by reference. Kadlec et al. disclose the generation of a cache enable signal by a second level cache to inhibit storing non-cacheable data in the second level cache. Other methods use an address decoder to distinguish between cacheable and non-cacheable address space. For example, U.S. Pat. No. 5,157,774, "System For Fast Selection of Non-cacheable Address Ranges Using Programmed Array Logic" (issued Oct. 1992 to Culley and assigned to Compaq Computer Corp.) discloses a cache that uses programmable array logic to decode address lines to distinguish between cacheable address space and non-cacheable address space, and is incorporated herein by reference. Other examples of address decoders which distinguish cacheable address space from non-cacheable address space are found in U.S. Pat. No. 5,045,998, "Method and Apparatus for Selectively Posting Write Cycles Using the 82385 Cache Controller" (issued Sep. 1991 to Begun et al. and assigned to International Business Machines Corp.); U.S. Pat. No. 5,125,084, "Control of Pipelined Operation in a Microcomputer System Employing Dynamic Bus Sizing with 80386 Processor and 82385 Cache Controller" (issued Jun. 1992 to Begun et al. and assigned to International Business Machines Corp.); U.S. Pat. No. 5,327,545, "Data Processing Apparatus for Selectively Posting Write Cycles Using the 82385 Cache Controller" (issued Jul. 1994 to Begun et al. and assigned to International Business Machines Corp.); U.S. Pat. No. 5,210,850, "Memory Address Space Determination Using Programmable Limit Registers with Single-ended Comparators (issued May 1993 to Kelly et al. and assigned to Compaq Computer Corp.); and U.S. Pat. No. 4,937,738, "Data Processing System Which Selectively Bypasses a Cache Memory in Fetching Information Based Upon Bit Information of an Instruction" (issued Jun. 1990 to Uchiyama et al. and assigned to Hitachi), which are all incorporated herein by reference. The prior art address decoders discussed above for distinguishing cacheable accesses from non-cacheable accesses all provide an output to the cache to determine whether or not action by the cache is needed.
The advantage that cache memory provides in a computer comes at the expense of more complex, hierarchal memory systems. Now a copy of data in system memory may exist in one or more levels of cache, requiring strict adherence to protocol to assure cache coherency, i.e., that identical data in each cache and in system memory are modified or invalidated to reflect the most recent change to the data. Assuring cache coherency requires the cache to monitor all accesses by the CPU to determine whether or not the access may be contained and actually is contained within the cache. Even when the access is to non-cacheable address space, prior art systems typically wait for the cache to respond with a miss before commencing a bus cycle to the non-cacheable address. The cache memory thus can impose a delay in non-cacheable accesses that would otherwise not be present.
Most microcomputer systems are expandable, allowing a user to add certain capabilities to the computer by plugging a circuit card into an expansion bus. Several different types of expansion busses are known, including PCI.RTM., Micro-Channel.RTM., ISA, and EISA. Expansion bus accesses are generally defined as non-cacheable. In addition, as stated above, certain portions of system memory also may be defined as non-cacheable. For a typical non-cacheable transfer in a typical prior art microcomputer system, the presence of the cache delays the access to the data. The processor first snoops the cache to determine whether the needed information is in the cache. A non-cacheable address will cause the cache memory to return a "miss." If the address is to non-cacheable memory, the memory controller performs a bus cycle to system memory to access the data. If the address is to the expansion bus, the expansion bus bridge performs the bus cycle on the expansion bus to access the data. The total access time to a non-cacheable address is therefore the sum of the time to generate a cache miss and the time for the memory controller or expansion bus bridge to generate the appropriate cycle to system memory or to the expansion bus, respectively. The access time to a non-cacheable address is therefore typically one to three clock cycles slower than the access time would be if the cache were not present due to the time required for the cache to signal a miss to the memory controller or expansion bus bridge. Thus we see that the advantages of a cache memory are partially offset by the slower access time to non-cacheable addresses. However, in most microcomputer systems, the number of accesses to cacheable address space is usually far greater than the number of accesses to non-cacheable address space. Thus, the advantage of the cache generally far outweighs the penalty incurred. However, it is clear that the performance of a microcomputer system could be enhanced by decreasing the access time for non-cacheable accesses.
Therefore, there existed a need to provide an apparatus and method for enhancing the performance of a microcomputer that has cache memory by decreasing the access time to non-cacheable address space, such as non-cacheable memory and the expansion bus.